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Welcome to the Fibonacci in Verilog page! Here, you'll find the source code for this program as well as a description of how the program works.
//Verilog code Listing first 25 Fibonacci numbers till module Fibonacci(); integer previous_value = 0; integer current_value = 1; integer clk = 0; always #1 clk = ~clk; always @(posedge clk) begin current_value <= current_value + previous_value; previous_value <= current_value; $display("%0d", current_value); end initial #50 //Prints 25 fibonacci numbers as values change at POSEDGE of clock $finish; endmodule
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