//Verilog code Listing first 25 Fibonacci numbers till module Fibonacci(); integer previous_value = 0; integer current_value = 1; integer clk = 0; always #1 clk = ~clk; always @(posedge clk) begin current_value <= current_value + previous_value; previous_value <= current_value; $display("%0d", current_value); end initial #50 //Prints 25 fibonacci numbers as values change at POSEDGE of clock $finish; endmodule
Fibonacci in Verilog was written by:
If you see anything you'd like to change or update, please consider contributing.
No 'How to Implement the Solution' section available. Please consider contributing.
No 'How to Run the Solution' section available. Please consider contributing.